Input pattern classification for transistor level testing of BiCMOS circuits
نویسندگان
چکیده
In BiCMOS, transi s t or s t uck-OPEN fault s exhi bi t del ay f aul t s i n addi t i on t o s equent i al behavi or . St uckON f aul t s caus e enhanced I DDQ. The f aul t y behavi or of Bi pol ar (TTL) and CMOS l ogi c f ami l i es i s compar ed wi t h Bi CMOS. The f aul t s i n Bi CMOS devi ces caus e one or more par t s ( ppar t or npar t s ) of t he ci r cui t t o ex hi bi t a di er ent s t at e ( conduct i ng or nonconduct i ng) f r omthe f aul t f r ee ci r cui i nput pat t ern cl as s i cat i on s cheme i s pr es ent ed f or di er ent f aul t s . Thes e cl as pat t erns ar e t hen us ed t o obt ai n t es t s et s .
منابع مشابه
Input Pattern Classification for Detection of Stuck-ON and Bridging Faults Using I/sub DDQ/ Testing in BiCMOS and CMOS Circuits
Quiescent power supply current monitoring (looa) has been shown to be effective for testing CMOS devices. BiCA4OS is emerging as a major technologv for high speed, high performance, digital and mixed signal applications. Stuck-ON faults as well as bridging faults in BiCMOS circuits cause enhanced IDDo. An input pattern classi$ation scheme is presented for detection of stuck-ONhridging faults ca...
متن کاملTestable Design of BiCMOS Circuits for Stuck-Open Fault Detection Using Single Patterns
Single BJT BiCMOS devices exhibit sequential behavior under transistor stuck-OPEN (+OPEN) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-OPEN faults exhibiting sequential behavior needs two-pattern or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented that uses only two ex...
متن کاملDesign-for-Testability Techniques for Detecting Delay Faults in CMOS/BiCMOS Logic Families
The delay fault testing in logic circuits is studied. It is shown that by detecting delayed time response in a transistor circuit, two types of faults are detected: 1) faults which cause delayed transitions at the output node due to some open defects and 2) faults which cause an intermediate voltage level at the output node. A test circuit is presented which enables the concurrent detection of ...
متن کاملA New True-Single-Phase-Clocking BiCMOS Dynamic Pipelined Logic Family for High-Speed, Low-Voltage P - Solid-State Circuits, IEEE Journal of
New true-single-phase-clocking (TSPC) BiCMOS/ BiNMOS/BiPMOS dynamic logic circuits and BiCMOS/BiNMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-full-swing operation. The circuit performance of the proposed new dynamic logic circuits and dynamic...
متن کاملHigh slew rate, low voltage BiCMOS and bipolar operational amplifier architectures with rail to rail - Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Class AB differential amplifiers using composite BiCMOS and bipolar transistors are introduced. Their utilization for the implementation of low voltage (+-1.65V) operational amplifiers with high slew rate and rail to rail common mode input voltage range is discussed.
متن کامل